The efficient multiple scan chain architecture reducing power dissipation and test time

The efficient use of unspecified bit in input test cube and its response test cube (henceforth, test set) reduces power dissipation and test time in the multiple scan chain architecture. First, unspecified bits in test set are clustered by reordering scan latches, and then the multiple scan chain architecture is modified by inserting multiplexers (MUXes) in each scan chain in order to implement the reordering for reduction of power and test time. Results with ISCAS´89 benchmark circuits show a good improvement in both power dissipation and test time.