New power index model for switching power analysis from adder graph of FIR filter

Efficient power modeling of a generic class of digital circuits is crucial to the analysis and development of optimization algorithms of power efficient design. This paper proposes a new switching power index model for the power analysis of multiplier-block based FIR filter. Unlike the existing glitch path count (GPC) and glitch path score (GPS), the proposed power index (PI) model takes into account correlated input switching activity propagations of full adders within and across adders of different widths, as well as the variation of load capacitances due to sharing of adders in reduced adder graph. Dynamic power simulations of several benchmark filters in an ASIC design flow show that this PI measure is more closely correlated with the actual dynamic power dissipation than the existing GPC and GPS models.