Device mismatch limitations on the performance of an associative memory system

Author

Kumar, Nagendra ; Pouliquen, Philippe O. ; Andreou, Andreas G.

Author_Institution

Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA

fYear

1993

fDate

16-18 Aug 1993

Firstpage

570

Abstract

The performance of an associative memory based computational engine that employs static binary memory cells and an analog Winner-Takes-All circuit depends on device matching in the various components of the system. This dependence has been analyzed, leading to design criteria for choosing optimum device sizes and chip architecture. The theoretical performance of a low power CMOS chip designed to operate in the subthreshold and transition region is compared with the actual experimental results

Keywords

CMOS memory circuits; content-addressable storage; integrated circuit design; analog winner-takes-all circuit; associative memory system; computational engine; design criteria; device mismatch limitations; low power CMOS chip; optimum chip architecture; optimum device sizes; static binary memory cells; Analog computers; Associative memory; Circuit testing; Computer architecture; Engines; Information processing; Latches; Power engineering computing; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on

Conference_Location

Detroit, MI

Print_ISBN

0-7803-1760-2

Type

conf

DOI

10.1109/MWSCAS.1993.342982

Filename

342982