Design of interleaved multithreading for Network Processors on Chip

Author

Freitas, Henrique C. ; Madruga, Felipe L. ; Alves, Marco A Z ; Navaux, Philippe O A

Author_Institution

Grad. Program in Comput. Sci., Inf. Inst., Univ. Fed. do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil

fYear

2009

fDate

24-27 May 2009

Firstpage

2213

Lastpage

2216

Abstract

Thread level parallelism and multi-core processors are current alternatives to increase performance of general-purpose applications. In the same way, networks-on-ohip (NoCs) are the main alternatives for supporting packet throughput for the next generations of many-core processors. NPoC (network processor on chip) is a proposal to increase the performance of programmable NoC routers and multi-cluster NoC architectures using interleaved multithreading (IMT) technique. Therefore, the main goal of this paper is to present the design impact of interleaved multithreading for network processors on chip focusing on area and performance feasibility. Results show that NPoC-based router has an acceptable and similar area relative to a conventional NoC, and higher performance up to 7.1% than the same NPoC version without IMT.

Keywords

microprocessor chips; multi-threading; network routing; network-on-chip; interleaved multithreading technique; multicluster networks-on-chip architectures; multicore processors; network processors on chip; programmable networks-on-ohip routers; thread level parallelism; Costs; Hardware; Multithreading; Network-on-a-chip; Parallel processing; Pipelines; Switches; Throughput; Wire; Yarn;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Conference_Location

Taipei

Print_ISBN

978-1-4244-3827-3

Electronic_ISBN

978-1-4244-3828-0

Type

conf

DOI

10.1109/ISCAS.2009.5118237

Filename

5118237