Speed-up of RISC processor computation using ADAPTO

In previous works ([1], [2] and [3]) the authors presented ADAPTO (adder-based dynamic architecture for processing tailored operators), a reconfigurable functional unit (RFU) that accelerates computations on data of shorter size than the native processor wordlength. ADAPTO is a reconfigurable array inserted directly in the data-path of the microprocessor in order to reduce the communication overhead between the reconfigurable unit and the microprocessor. An important feature of ADAPTO is the capacity to reconfigure itself and execute operations in one clock cycle. ADAPTO, differently from other architectures presented in the literature ([6] [7]) is based on full-adders (FA) instead of LUTs. The FA can be configured to perform logical and arithmetical operations with the advantage of a less number of transistors than in the case of a LUT approach. In this paper we show how ADAPTO increases the performance of a RISC processor in the executions of algorithm processing short size data.