Improving the hardware utilization efficiency of partially parallel LDPC decoder with scheduling and sub-matrix decomposition

Partially parallel LDPC decoder is commonly used for practical applications due to its good tradeoff between the hardware cost and the throughput. In the partially parallel LDPC decoding architecture, two kinds of processor units are implemented: check node unit (CNU) and variable node unit (VNU). Because of the dependency between two kinds of processor units, the low hardware utilization efficiency (HUE) is one of the design issues for the partially parallel decoding architecture. In order to achieve the optimal hardware utilization efficiency, it is important to determine the order of the rows and columns in the LDPC parity check matrix processed by the processor units. In this paper, we model the scheduling problem as an optimization problem and use simulated annealing to find good solutions for the scheduling. In order to further increase the HUE of the partially parallel decoding architecture, sub-matrix decomposition scheme is proposed. By applying these two schemes, the HUE of some partially parallel decoding implementations can achieve 100%.