Title :
High throughput architecture for high performance NoC
Author :
Abd El Ghany, Mohamed A. ; El-Moursy, Magdy A. ; Ismail, Mohammed
Author_Institution :
Electron. Eng. Dept., German Univ. in Cairo, Cairo, Egypt
Abstract :
High throughput butterfly fat tree (HTBFT) architecture to achieve high performance networks on chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to butterfly fat tree switch. The total metal resources required to implement HTBFT design is increased by 5% as compared to the total metal resources required to implement BFT design. The extra power consumption required to achieve the proposed architecture is 3% of the total power consumption of the BFT architecture.
Keywords :
hypercube networks; network-on-chip; power consumption; NoC; average latency; extra power consumption; high throughput butterfly fat tree architecture; metal resources; networks on chip; Decoding; Delay; Energy consumption; Frequency; Integrated circuit interconnections; Multiplexing; Network-on-a-chip; Switches; Switching circuits; Throughput; BFT; Latency; NoC; Throughput;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118244
