DocumentCode :
2262020
Title :
Design of self-checking circuits for unsystematic codes
Author :
Bohlau, Peter
Author_Institution :
Potsdam Univ., Germany
fYear :
1993
fDate :
16-18 Aug 1993
Firstpage :
542
Abstract :
A new algorithm is proposed for the design of self-checking circuits for a new subset of codes. A classification of the synthesis methods based on the property of groupability of Boolean functions is described. In this paper is presented a new method for the systematic design of self-checking code error detecting circuits with 100% fault coverage for single stuck-at-faults. The new algorithm for the systematic design of an optimal on-line error detecting circuit is based on functional properties and on the functional decomposition. The property of groupability of Boolean functions is used for a selective algorithm based on Boolean differential operations. We can test these properties for any function K by Boolean differential equations in a maximal operation complexity of O(n2) where n is the number of code variables. For example, it is proved, that 50% of all Boolean functions are multiple antivalent groupable. In the presentation the development of code error detecting self-checking circuits is described for unsystematic codes, i.e. the design of self-checking two-rail checkers for antivalent groupable codes K and the design of self-checking multi-rail checkers for conjunctive groupable codes K with a self-checking comparator. The objective of the new approach is to minimize the gate area of the chip. The result of the approach is, that the gate area is approximately 40% lower than by using the method of on-line error detection by duplication and comparison of the self-checking checker
Keywords :
Boolean functions; automatic testing; error detection; logic design; logic testing; Boolean differential operations; Boolean functions; chip gate area; code error detecting circuits; functional decomposition; groupability; maximal operation complexity; optimal online error detecting circuit; self-checking circuits; single stuck-at-faults; synthesis methods; two-rail checkers; unsystematic codes; Algorithm design and analysis; Boolean functions; Built-in self-test; Circuit faults; Circuit synthesis; Circuit testing; Differential equations; Electrical fault detection; Fault detection; Fault tolerance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-1760-2
Type :
conf
DOI :
10.1109/MWSCAS.1993.343000
Filename :
343000
Link To Document :
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