Partitioned and parallel cyclic redundancy checking

Author

Sobski, Andrzej ; Albicki, A.

Author_Institution

Dept. of Electr. Eng., Rochester Univ., NY, USA

fYear

1993

fDate

16-18 Aug 1993

Firstpage

538

Abstract

In this paper, the linear feedback shift register (LFSR) is redesigned to process several bits of a long data stream simultaneously in order to obtain a signature more quickly. The resulting structure is capable of encoding, decoding, detecting, and correcting errors in cyclic codes partitioned into variable length words; hence, it is given the name partitioned parallel encoder, decoder, detector, corrector (pPEDDC). A simple pPEDDC VLSI chip has been fabricated and used to extract performance measures for comparison with equivalent LFSR implementations

Keywords

VLSI; computer networks; cyclic codes; decoding; error correction; error detection; integrated logic circuits; parallel architectures; redundancy; shift registers; VLSI chip; cyclic codes; decoding; encoding; error correction; error detection; linear feedback shift register; parallel cyclic redundancy checking; partitioned parallel scheme; variable length words; Cyclic redundancy check; Data mining; Decoding; Detectors; Encoding; Error correction; Error correction codes; Flip-flops; Linear feedback shift registers; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on

Conference_Location

Detroit, MI

Print_ISBN

0-7803-1760-2

Type

conf

DOI

10.1109/MWSCAS.1993.343001

Filename

343001