Pair balance-based test scheduling for SOCs

Along with more pre-designed and pre-verified cores are integrated into a single chip to construct an entire system, the test application time increases significantly. This paper presents a novel test scheduling solution, unlike previous techniques that take advantage of balanced scan chains of every single core, utilizing the balance of pairwise combined cores. Experimental results for two ITC ´02 SOC benchmarks show that the pair balance-based test scheduling technique achieves less test time compared to the previous approaches.