Berger code self-testing checkers with partitioning and folding scheme

Due to the salient feature of the least redundant separable codes, Berger codes have been implemented for fault-tolerant, fail-safe, and concurrent error testable designs of digital circuits and systems. The features of high speed and low hardware cost are highly desirable, especially for a checker design. A fast self-testing checker (STC) design of Berger code implemented with partitioning scheme has been proposed recently. The design offers an improvement in delay, but still high hardware overhead. In this paper, an alternative partitioning scheme manipulating the most significant check bit is proposed. Results show that, implementing with the proposed partitioning scheme, the number of m/n sub-checkers required in a STC design can be reduced by half, and the hardware reduction can be as much as 50%