• DocumentCode
    2262108
  • Title

    RAIN (RAndom INsertion) scheduling algorithm for SoC test

  • Author

    Im, Jung-Been ; Chun, Sunghoon ; Kim, Geunbae ; An, Jin-Ho ; Kang, Sungho

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Yonsei Univ. Seoul, South Korea
  • fYear
    2004
  • fDate
    15-17 Nov. 2004
  • Firstpage
    242
  • Lastpage
    247
  • Abstract
    This paper presents a new SoC (system-on-chip) test scheduling algorithm. Reducing the test application time is an important issue for a core-based SoC test. In this paper, each core is represented by a rectangle, the height of which is equal to the TAM width and the width of which is equal to the test time. A ´one-element-exchange´ algorithm is used for optimizing the test time of each core and the ´RAIN´ scheduling algorithm is used for optimizing the test time of SoC. The RAIN scheduling algorithm uses a sequence pair data structure to represent the placement of rectangles, and obtains the optimized results by inserting into a random position on the sequence pair. The results of the experiments conducted using ITC ´02 SoC benchmarks show that the proposed algorithm gives the shortest test application time compared with earlier researches for most of the cases.
  • Keywords
    circuit optimisation; integrated circuit layout; integrated circuit testing; system-on-chip; ITC 02 SoC benchmarks; RAIN scheduling algorithm; SoC test time optimization; SoC testing; one-element-exchange algorithm; sequence pair data structure; system-on-chip test scheduling algorithm; test access mechanism; Design for testability; Design optimization; Electronic equipment testing; Logic design; Logic testing; Partitioning algorithms; Pins; Rain; Scheduling algorithm; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2004. 13th Asian
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-2235-1
  • Type

    conf

  • DOI
    10.1109/ATS.2004.71
  • Filename
    1376565