• DocumentCode
    2262116
  • Title

    March based memory core test scheduling for SOC

  • Author

    Wang, Wei-Lun

  • Author_Institution
    Cheng Shiu Univ., Kaohsiung, Taiwan
  • fYear
    2004
  • fDate
    15-17 Nov. 2004
  • Firstpage
    248
  • Lastpage
    253
  • Abstract
    To implement the complicated functionality, the number of required embedded memory cores in a system-on-chip (SOC) is growing more and more. How to reduce the testing time of the multiple memory cores under the power constraint of SOC becomes an important issue. Based on the march elements of the march algorithms, an effective method for the embedded memory core test scheduling is presented in this paper. Without losing the memory testing functionality, the march elements of a march algorithm can be performed consecutively by distinct test resources. This gives a great flexibility in the proposed march element based test scheduling method to reduce the overall testing time of the multiple memory cores. To reduce the total testing cost, appropriate resources should be considered in the test scheduling. In this paper, several experiments have shown that the utilization of test resources and testing time reduction by using the proposed method.
  • Keywords
    CMOS memory circuits; electronic engineering computing; integrated circuit design; integrated circuit testing; integrated memory circuits; scheduling; system-on-chip; embedded memory cores; march algorithms; memory core test scheduling; memory testing functionality; power constraint; system-on-chip; test resources; testing time; Built-in self-test; Capacitance; Circuit testing; Costs; Degradation; Delay effects; Leakage current; Performance evaluation; Read-write memory; Scheduling algorithm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 2004. 13th Asian
  • ISSN
    1081-7735
  • Print_ISBN
    0-7695-2235-1
  • Type

    conf

  • DOI
    10.1109/ATS.2004.56
  • Filename
    1376566