Optimum area minimization for nonslicing floorplan [VLSI layout]

In this paper, we propose a new algorithm to solve the floorplan area optimization problem for all implementations of each module. By using slicing and extended slicing techniques, we decompose a complicated floorplan into basic L-shape and rectangular blocks in top-down manner and then combine them in bottom-up manner. Experimental results show that our algorithm is very efficient and capable of handling large floorplan compared to some existing ones