DocumentCode :
2262148
Title :
Nonbinary Convolutional Encoder for Vector Symbol Decoding on FPGA board
Author :
Tuntoolavest, Usana ; Intharasakul, Rachanon
Author_Institution :
Dept. of Electr. Eng., Kasetsart Univ., Bangkok
fYear :
2006
fDate :
27-30 Nov. 2006
Firstpage :
1
Lastpage :
4
Abstract :
Convolutional codes are widely used for reliable data communications. Conventionally, the codes use binary symbols because their decoders such as Viterbi decoder or sequential decoder usually were designed for binary symbols. In order to develop the system for nonbinary convolutional codes that use the vector symbol decoding algorithm, there is a need for a nonbinary convolutional encoder that works with large symbol size since the typical size of this decoding algorithm is 32 bits/symbol. For ease of implementation, this encoder was developed on an FPGA (field programmable gate array) board.
Keywords :
binary codes; channel coding; convolutional codes; decoding; field programmable gate arrays; FPGA board; binary symbol; channel code decoding technique; convolutional codes; nonbinary convolutional encoder; vector symbol decoding algorithm; Circuits; Convolutional codes; Data engineering; Decoding; Encoding; Field programmable gate arrays; Hardware design languages; Switches; Universal Serial Bus; Viterbi algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communication Technology, 2006. ICCT '06. International Conference on
Conference_Location :
Guilin
Print_ISBN :
1-4244-0800-8
Electronic_ISBN :
1-4244-0801-6
Type :
conf
DOI :
10.1109/ICCT.2006.341780
Filename :
4146381
Link To Document :
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