Bridging technology-CAD and design-CAD for variability aware Nano-CMOS circuits

Transistor variability has emerged as one of the important constraints in Nano-CMOS circuit design. The ever decreasing device feature size with CMOS scaling, has resulted in an increasing uncertainty in predicting the exact device behaviour. The issue of variability needs to be addressed across the entire hierarchy of integrated circuits - optimization of process and device technology to yield minimal variability, robust circuit and system design architectures for variability aware design, and CAD tools to unify these two domains. The traditional variability modeling and CAD techniques address the problem in one of the two domains. We propose a unified framework to bridge the gap between technology CAD and design CAD. This framework enables one to directly relate the variation in circuit metrics such as speed, static power and dynamic power to the underlying semiconductor process parameters such as implant dose, annealing temperature etc. The proposed methodology is validated through rigorous simulations at the process, device and circuit level, incorporating various statistical techniques. A few examples will be presented to elaborate the significance of the proposed modeling methodology and its utility in the Nano CMOS design flow. In addition to being an important utility in the circuit design flow, the methodology will also help the foundries by providing a visibility on the impact of unit processes on the eventual circuit characteristics. This in turn can help in a systematic and optimized process monitoring in the foundries.