Power reduction of ASIPs by distributing the workload on several ASIP-instances

In modern SoC designs, more and more application specific instruction-set processors (ASIPs) are used. They enable a trade off between the flexibility due to the software implementation of algorithms and hardware efficiency arising from the ASIP architecture which is optimized with respect to the application. In this paper, it is shown that the total power dissipation could be reduced by distributing the software tasks on several identical ASIP instances although the throughput of a single ASIP would be sufficient for all tasks. In addition, it is shown that for power comparisons of processor instances, the number of executed lines of code is a parameter which gives more insight into power comparisons than the clock rate.