Topological design of clock distribution networks based on non-zero clock skew specifications

A methodology is presented in this paper for designing clock distribution networks based on application dependent clock skew information. Contrary to previous approaches, the clock distribution network is designed such that the clock skew between two sequentially adjacent registers can be non-zero in order to maximize synchronous performance. The clock skew information is used to define the network topology and determine the delay values of the network branches. The design strategy for determining the topology of the clock distribution network considers the hierarchical description of the circuit to define the branching points of the clock tree. Algorithms to determine the optimal clock delay to each register and the network topology, given the non-zero clock skew specifications, are described and clock distribution networks are developed for example circuits