Burn-in stress test of analog CMOS ICs

Author

Wey, Chin-Long ; Liu, Meng-Yao

Author_Institution

Dept. of Electr. Eng., National Central Univ., Chung-Li, Taiwan

fYear

2004

fDate

15-17 Nov. 2004

Firstpage

360

Lastpage

365

Abstract

With the successful development of EVoSTA (Extreme-Voltage Stress Test for Analog CMOS ICs), this paper investigated whether the extreme-temperature burn-in stress test is properly applied for enhancing the gate-oxide reliability of mixed-signal/analog CMOS ICs. Burn-in is an effective screening method used in predicting, achieving, and enhancing field reliability of ICs. Today, almost all IC manufacturers perform 100% burn-in for various durations to screen defective products. However, the major problems associated with burn-in are the determination of exactly how long the burn-in process should continue, balancing appropriately the needs of reliability and the total costs, and what stress vectors should be applied? This paper conducted a feasibility study for resolving such issues.

Keywords

CMOS analogue integrated circuits; analogue integrated circuits; integrated circuit reliability; integrated circuit testing; EVoSTA; analog CMOS IC; burn-in process; extreme-temperature burn-in stress test; extreme-voltage stress test for analog cmos ic; field reliability; gate-oxide reliability; mixed-signal CMOS IC; screen defective products; screening method; Application specific integrated circuits; Costs; Electromigration; Failure analysis; Foundries; Hot carriers; Integrated circuit interconnections; Manufacturing; Stress; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 2004. 13th Asian

ISSN

1081-7735

Print_ISBN

0-7695-2235-1

Type

conf

DOI

10.1109/ATS.2004.28

Filename

1376585