An all-digital phase-locked loop for digital power management integrated chips

Author

Chung, Yu-Ming ; Wei, Chia-Ling

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

2009

fDate

24-27 May 2009

Firstpage

2413

Lastpage

2416

Abstract

An all-digital phase-locked loop (ADPLL) for digital power management applications is presented. The conventional RC loop filter is replaced by a digital loop filter, and the conventional analog voltage-controlled oscillator (VCO) is replaced by a digitally controlled oscillator (DCO). The design procedure of the presented ADPLL is similar to the design procedure of a conventional type-square, second-order charge-pump PLL. The ADPLL was implemented by the TSMC 0.18-mum CMOS process, and the measured DCO oscillating frequency range is 87-250 MHz.

Keywords

CMOS digital integrated circuits; VHF oscillators; digital filters; digital phase locked loops; ADPLL design; DCO oscillating frequency; TSMC CMOS process; all-digital phase-locked loop; digital loop filter; digital power management applications; digital power management integrated chip; digitally controlled oscillator; frequency 87 MHz to 250 MHz; size 0.18 mum; CMOS process; Charge pumps; Digital control; Digital filters; Energy management; Frequency measurement; Phase locked loops; Radio control; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Conference_Location

Taipei

Print_ISBN

978-1-4244-3827-3

Electronic_ISBN

978-1-4244-3828-0

Type

conf

DOI

10.1109/ISCAS.2009.5118287

Filename

5118287