A fold-back current-limit circuit with load-insensitive quiescent current for CMOS low dropout regulator

Author

Guo, Jianping ; Leung, Ka Nang

Author_Institution

Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Hong Kong, China

fYear

2009

fDate

24-27 May 2009

Firstpage

2417

Lastpage

2420

Abstract

A fold-back current-limit circuit, with load-insensitive quiescent current characteristic for CMOS low dropout regulator (LDO), is proposed in this paper. This method has been designed in 0.35 mum CMOS technology and verified by Hspice simulation. The quiescent current of the LDO is 5.7 mA at 100-mA load condition. It is only 2.2% more than it in no-load condition, 5.58 mA. The maximum current limit is set to be 197 mA, and the short-current limit is 77 mA. Thus, the power consumption can be saved up to 61% at the short-circuit condition, which also decreases the risk of damaging the power transistor. Moreover, the thermal protection can be simplified and the LDO will be more reliable.

Keywords

CMOS integrated circuits; low-power electronics; short-circuit currents; transient response; voltage regulators; CMOS low dropout regulator; Hspice simulation; current 100 mA; current 197 mA; current 5.58 mA; current 5.7 mA; current 77 mA; fold-back current-limit circuit; load-insensitive quiescent current; power consumption; power transistor; short-circuit condition; size 0.35 mum; thermal protection; CMOS technology; Circuit simulation; Costs; Energy consumption; MOSFETs; Power transistors; Regulators; Resistors; Temperature dependence; Temperature sensors;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Conference_Location

Taipei

Print_ISBN

978-1-4244-3827-3

Electronic_ISBN

978-1-4244-3828-0

Type

conf

DOI

10.1109/ISCAS.2009.5118288

Filename

5118288