Device resizing based optimization of analog circuits for reduced test cost: cost metric and case study

In this paper a cost metric has been proposed, which can drive device resizing during circuit design with the objective of efficient low-cost production test of analog circuits. A test cost reduction method using dynamic and selective elimination of specification tests for fault-free circuits has also been proposed. The test elimination method exploits correlations between analog specifications. Higher correlation allows one specification to be tested (without performing measurements) against its acceptability limits by analyzing measurement data corresponding to the other correlated specification. The proposed cost metric can be imported into any typical device-resizing algorithm used in analog synthesis tools, which try to optimize circuit performance and manufacturing yield. Simulation results using op-amps show the feasibility and the effectiveness of the proposed cost metric.