Title :
Alternative run-length coding through scan chain reconfiguration for joint minimization of test data volume and power consumption in scan test
Author :
Shi, Youhua ; Kimura, Shinji ; Togawa, Nozomu ; Yanagisawa, Masao ; Ohtsuki, Tatsuo
Author_Institution :
Dept. of Comput. Sci., Waseda Univ., Tokyo, Japan
Abstract :
Test data volume and scan power are two major concerns in SoC test. In this paper we present an alternative run-length coding method through scan chain reconfiguration to reduce both test data volume and scan-in power consumption. The proposed method analyzes the compatibility of the internal scan cells for a given test set and then divides the scan cells into compatible classes. To extract the compatible scan cells we apply a heuristic algorithm by solving the graph coloring problem; and then a simple greedy algorithm is used to configure the scan chain for the minimization of scan power. Experimental results for the larger ISCAS´89 benchmarks show that the proposed approach leads to highly reduced test data volume with significant power savings during scan test.
Keywords :
boundary scan testing; data reduction; encoding; graph colouring; greedy algorithms; heuristic programming; minimisation; system-on-chip; ISCAS89 benchmarks; SoC testing; compatible scan cells extraction; graph coloring problem; heuristic algorithm; joint minimization; run-length coding; scan chain reconfiguration; scan power minimization; scan test; scan-in power consumption; simple greedy algorithm; test data volume; Computer science; Data mining; Energy consumption; Greedy algorithms; Heuristic algorithms; Minimization methods; Production systems; System testing; System-on-a-chip; Test data compression;
Conference_Titel :
Test Symposium, 2004. 13th Asian
Print_ISBN :
0-7695-2235-1
DOI :
10.1109/ATS.2004.21