Title :
A postprocessing procedure of test enrichment for path delay faults
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
Test sets for path delay faults in circuits with large numbers of paths are typically generated for faults associated with the longest circuit paths. Such test sets may not detect faults associated with the next-to-longest paths. This may lead to undetected failures. A dynamic test enrichment procedure proposed earlier increases the number of faults associated with the next-to-longest paths that are detected by a test set in order to improve its quality without increasing its size. The earlier procedure is referred to as dynamic since the decision as to which faults associated with next-to-longest paths will be detected is done during test generation. In this work, we describe a postprocessing procedure for test enrichment that accepts a given test set. By processing the tests in reverse order, the proposed procedure increases the number of detected faults associated with next-to-longest paths without increasing the number of tests. We demonstrate the effectiveness of the proposed reverse order test enrichment procedure when applied following, and instead of dynamic test enrichment.
Keywords :
automatic test pattern generation; circuit analysis computing; delay circuits; fault diagnosis; integrated circuit testing; fault detection; path delay faults; test enrichment postprocessing procedure; test generation; undetected failures; Circuit faults; Circuit testing; Cities and towns; Delay; Electrical fault detection; Fault detection; Performance analysis; Timing; Virtual manufacturing;
Conference_Titel :
Test Symposium, 2004. 13th Asian
Print_ISBN :
0-7695-2235-1
DOI :
10.1109/ATS.2004.14