DocumentCode :
2263058
Title :
A partitioning technique for identification of error-capturing scan cells in scan-BIST
Author :
Yu, Chaowen ; Reddy, Sudhakar M. ; Pomeranz, Irith
Author_Institution :
Dept. of ECE, Iowa Univ., IA
fYear :
0
fDate :
0-0 0
Abstract :
The paper proposes a two-step scan cell partitioning scheme to identify the error-capturing scan cells in a scan-BIST environment. In the first step, a deterministic partitioning scheme is used, whose target is to maximize the correlations between different scan cells in fault diagnosis since different scan cells have very different probabilities of capturing fault effects. In the second step, a previously proposed random partitioning scheme is used to generate additional partitions. Experimental results are reported on the five largest ISCAS´89 benchmark circuits and compared with that for the random partitioning scheme and another earlier work using interval-based partitioning scheme
Keywords :
boundary scan testing; built-in self test; integrated circuit testing; logic partitioning; logic testing; deterministic partitioning scheme; error capturing scan cells; fault diagnosis; fault effects; random partitioning scheme; scan cell partitioning scheme; scan-BIST; Automatic testing; Built-in self-test; Chaos; Circuit faults; Circuit testing; Cities and towns; Design for testability; Fault diagnosis; Integrated circuit testing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International
Conference_Location :
Lake Como
Print_ISBN :
0-7695-2620-9
Type :
conf
DOI :
10.1109/IOLTS.2006.9
Filename :
1655513
Link To Document :
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