VLSI design of sequential minimal optimization algorithm for SVM learning

Author

Kuan, Ta-Wen ; Wang, Jhing-Fa ; Wang, Jia-Ching ; Gu, Gaung-Hui

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

2009

fDate

24-27 May 2009

Firstpage

2509

Lastpage

2512

Abstract

The sequential minimal optimization (SMO) algorithm has been widely used for training the support vector machine (SVM). In this paper, we present the first chip design for sequential minimal optimization. This chip is implemented as an intellectual property (IP) core, suitable to be utilized in an SVM-based recognition system on a chip. The proposed SMO chip has been tested to be fully functional, using a prototype system based on the Altera DE2 board with Cyclone II 2C70 FPGA (field-programmable gate array).

Keywords

VLSI; circuit analysis computing; field programmable gate arrays; industrial property; integrated circuit design; learning (artificial intelligence); optimisation; support vector machines; Cyclone II 2C70 FPGA; SVM learning; SVM-based recognition system; VLSI design; field-programmable gate array; intellectual property; sequential minimal optimization algorithm; support vector machine; Algorithm design and analysis; Chip scale packaging; Cyclones; Design optimization; Field programmable gate arrays; Intellectual property; Prototypes; Support vector machines; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Conference_Location

Taipei

Print_ISBN

978-1-4244-3827-3

Electronic_ISBN

978-1-4244-3828-0

Type

conf

DOI

10.1109/ISCAS.2009.5118311

Filename

5118311