Title :
Efficient implementation of the two dimensional discrete cosine transform for image coding applications on the DSP96002 processor
Author :
Ramaswamy, Srinath V. ; Miller, Gerald D.
Author_Institution :
Dept. of Electr. Eng., Northern Illinois Univ., DeKalb, IL, USA
Abstract :
This paper describes the efficient implementation of the 2D DCT for image coding on the DSP96002 processor. The DSP96002 is a general purpose, dual-bus IEEE floating point digital signal processor. Utilizing the DSP96002´s inherent parallel processing capabilities, the execution of a 8×8 fast 2D DCT takes 133 microseconds. The recently proposed 2D and 1D fast DCT algorithms are employed in this implementation. Transform coefficient zigzag ordering, used in the image coding process, executes in less than 28 microseconds. The fast DSP96002 routines, incorporated within this implementation, can be applied in a number of image coding applications such as video and still image coding as well as the newer JPEG still image and MPEG video standards
Keywords :
digital signal processing chips; discrete cosine transforms; floating point arithmetic; image coding; parallel processing; 133 mus; 28 mus; 2D DCT; DSP96002 processor; discrete cosine transform; dual-bus IEEE floating point DSP; image coding applications; parallel processing capabilities; transform coefficient zigzag ordering; two dimensional DCT; Digital signal processing chips; Digital signal processors; Discrete cosine transforms; Discrete transforms; Image coding; Signal processing algorithms; Speech processing; Transform coding; Video compression; Video signal processing;
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-1760-2
DOI :
10.1109/MWSCAS.1993.343057
