Test challenges for 3D circuits

Summary form only given. It is amazing how chip level integration has progressed to this point that we now have chips that consist of more than a billion transistors. As amazing as this level of integration, we have only been exploiting 2 dimensions (2D) integration only, i.e. transistors are still on a common plane. Obviously, one way to surpass this 2D integration trend is to go three dimensions (3D). The multiple layers of metal interconnects does not qualify as 3D as the transistors are still on the same plane. Common perception is that 3D simply means die stacking, with peripheral wire bonding to connect individual chips to a common substrate. Technology has advanced beyond that. Wafer thinning and tiny through silicon via (TSV) technology that intimately interconnects 2 or more pieces of silicon are commercially available. This has opened up the space for more advanced level of 3D integration. Dies can literally be stacked one on top of each other with potentially millions of tiny pads that bond the 2 dies together. Since circuits can be placed closer together (on top of each other), wire length is reduced and more importantly wire loading is also reduced, leading to better performance and reduced power consumption. Of course, this poses many issues, not the least is the challenge of testing partial circuits at the wafer level. Since the circuits are not completed before the 2 dies are fused together, the circuitry on either wafer/die are only partial and incomplete. How would we implement any kind of functional test (which may be needed for better pairing of defect free dies or dies that has similar process characteristics)? What about structural test (with all these dangling nodes off millions of these tiny vias/pads? What about the clock and power network which may be split between the 2 dies (which is essentially incomplete structure on their individual wafer)? This is very different than the known good die (KGD) problem in the past as the dies are only pa- - rtial. If we had problems with KGD in the past (to support multiple chip module (MCM)), how would we expect to be able to support this new level of integration? If we leave the partial dies relatively untested, what would be the resulting yield? What would be the resulting performance of the die stack? This talk highlights the test challenges associated with an advanced version of 3D integration