A high-precision low-voltage low dropout regulator for SoC with adaptive biasing

A high-precision low-voltage low dropout regulator (LDR) using adaptive biasing to extend the loop bandwidth is proposed for system-on-chip power management applications. The multi-stage output-capacitor-free LDR is stabilized by miller compensation and Q-reduction technique to reduce the requirement of minimum load current. By using direct current feedback from a simple current mirror, the adaptively-biased LDR achieves higher loop bandwidth, faster load and line transient responses, higher power supply rejection and lower output impedance. The load and line regulations are also improved. Designed in a standard 0.35 mum CMOS technology (V_tnap 0.52 V and V_tpap -0.72 V), the 1.2 V input 1.0 V output LDR requires a minimum load current of 50 muA and delivers a maximum current of 100 mA. Both theoretical analysis and simulation results are presented to demonstrate the advantages of the proposed LDR.