Fault tolerance implementation within SRAM based FPGA designs based upon the increased level of single event upset susceptibility

Emerging technology is enabling the design community to consistently expand the amount of functionality that can be implemented within integrated circuits (ICs). As the number of gates placed within an FPGA increases, the complexity of the design can grow exponentially. Consequently, the ability to create reliable circuits has become an incredibly difficult task. In order to ease the complexity of design completion, the commercial design community has developed a very rigid (but effective) design methodology based on synchronous circuit techniques. In order to create faster, smaller and lower power circuits, transistor geometries and core voltages have decreased. In environments that contain ionizing energy, such a combination increase the probability of single event upsets (SEUs) and consequently affect the state space of a circuit. In order to combat the effects of radiation, the aerospace community has developed several "hardened by design" (fault tolerant) design schemes. This paper addresses design mitigation schemes targeted for SRAM based FPGA CMOS devices. Because some mitigation schemes may be over zealous (too much power, area, complexity, etc...), the designer should be conscious that system requirements can ease the amount of mitigation necessary for acceptable operation. Therefore, various degrees of fault tolerance is demonstrated along with an analysis of its effectiveness