DocumentCode
2263275
Title
Sub-threshold circuit design with shrinking CMOS devices
Author
Calhoun, Benton H. ; Khanna, Sudhanshu ; Mann, Randy ; Wang, Jiajing
Author_Institution
Charles L. Brown Dept. of Electr. & Comput. Eng., Univ. of Virginia, Charlottesville, VA, USA
fYear
2009
fDate
24-27 May 2009
Firstpage
2541
Lastpage
2544
Abstract
This paper examines the impact of technology scaling to 22 nm on sub-threshold circuit design and proposes several solutions for sub-threshold circuits in new processes. To maintain energy-efficient sub-threshold operation, we must reduce variation and suppress leakage current. To combat random variation and minimize energy for nodes below 45 nm, we show that special strategies are needed for different categories of sub-threshold circuits.
Keywords
CMOS integrated circuits; integrated circuit design; leakage currents; energy-efficient subthreshold operation; leakage current; shrinking CMOS devices; size 22 nm; subthreshold circuit design; CMOS process; CMOS technology; Circuit synthesis; Energy consumption; Energy efficiency; Leakage current; Predictive models; Robustness; Semiconductor process modeling; Space technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location
Taipei
Print_ISBN
978-1-4244-3827-3
Electronic_ISBN
978-1-4244-3828-0
Type
conf
DOI
10.1109/ISCAS.2009.5118319
Filename
5118319
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