Combinational logic soft error analysis and protection

Soft errors in combinational logic are increasingly contributing to the systems´ failure rate and need to be addressed to ensure dependable operation of an IC. This paper presents first a new method for soft error analysis of combinational logic, second a method for increasing the robustness of combinational logic and third a software tool implementation for performing these operations on Verilog netlists in an automated way with minimum impact on performance. It is shown on ISCAS ´85 benchmarks that it is possible to reduce the soft error sensitivity by more than 60% at the cost of 20% in area with a design solution using only standard library cells. Further reduction in area cost is possible when applying the proposed method to the internals of standard library cells. In contrast to transistor sizing approaches, the proposed method benefits from the smaller feature sizes of newer IC process technologies