Subthreshold deep submicron performance investigation of CMOS and DTCMOS biasing schemes for reconfigurable computing

This paper investigates subthreshold CMOS logic for ultra low power applications on next generation reconfigurable devices. The performance characteristics of key digital building blocks such as arithmetic units, multiplexers and look-up-tables have been analyzed in terms of speed, power dissipation and power delay product using Berkeley predictive technology models at 22 nm technology node for both the conventional subthreshold CMOS (CMOS) and the dynamic threshold subthreshold CMOS (DTCMOS). Simulation results show that DTCMOS has lower PDP and sensitivities to process variations compared to CMOS for the digital blocks. Moreover, the PDP of blocks can be further improved by using longer channel lengths.