The structure and application of a new multi-DSP parallel computing architecture based on ADSP-2106x

Conventional radar signal processing systems have very limited flexibility because they are designed for their specific applications. For this problem, a general purpose high-speed radar signal processing system based on parallel computer architecture may be a hopeful solution. One of the key components in such a system is the processing node, which is chiefly responsible for the computation-intensive tasks. This paper presents a scheme of the processing node using a new multi-DSP parallel computing architecture as the hardware core. This architecture consists of five ADSP-2106x chips. It has many promising characteristics such as strong computational capability, broad I/O bandwidth, various communication methods, topology flexibility, and good expansion capability