Title :
Analysis and design of ultra-low power subthreshold MCML gates
Author :
Alioto, Massimo ; Leblebici, Yusuf
Author_Institution :
Dept. of Inf. Eng., Univ. of Siena, Siena, Italy
Abstract :
In this paper, ultra-low power current-mode subthreshold MOS current-mode logic (MCML) gates are discussed from a modeling and design perspective. A detailed analysis of the DC characteristics is presented, and the effect of process variations is analyzed in depth. Analysis allows for understanding the main limits of sub-threshold MCML gates in terms of delay/power variability. In particular, it is shown that process variations strongly affect the DC characteristics, and moderately impact delay and power consumption. Interestingly, delay and power variations are shown to be significantly reduced compared to typical values encountered in standard subthreshold CMOS logic. Criteria to size transistors to keep variations within assigned bounds are also derived. Results of Monte Carlo simulations with a 65-nm CMOS technology are reported to validate theoretical results.
Keywords :
CMOS logic circuits; Monte Carlo methods; current-mode logic; logic gates; low-power electronics; MOS current-mode logic gates; Monte Carlo simulation; delay-power variability; power consumption; size 65 nm; standard subthreshold CMOS logic; ultra-low power subthreshold MCML gates; CMOS logic circuits; CMOS technology; Delay; Design engineering; Energy consumption; Information analysis; Logic circuits; MOSFETs; Semiconductor device modeling; Threshold voltage;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118323
