Title :
A VLSI multistreaming RISC processor
Author :
Choe, Swee-yew ; Chan, Choong-wah ; Chua, Hong-chuek
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore
Abstract :
A multistreaming RISC processor for image processing implemented in VLSI is described. Multistreaming overcomes data and control dependencies inherent in pipeline execution. This approach is well suited for image processing where the availability of multiple independent tasks allows the pipeline to maintain its maximum throughput
Keywords :
VLSI; digital signal processing chips; image processing; image processing equipment; pipeline processing; reduced instruction set computing; VLSI; image processing; maximum throughput; multiple independent tasks; multistreaming RISC processor; pipeline execution; Decoding; Hazards; Image processing; Pipelines; Read-write memory; Reduced instruction set computing; Registers; Streaming media; Throughput; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-1760-2
DOI :
10.1109/MWSCAS.1993.343071
