Title :
A VLSI architecture for DFT
Author :
Chan, Eric ; Panchanathan, Sethuraman
Author_Institution :
Dept. of Electr. Eng., Ottawa Univ., Ont., Canada
Abstract :
In this paper, a one-dimensional fully pipelined architecture for computing discrete-Fourier transform (DFT) is presented. It consists of an array of N basic cells (BC´s) and requires N clock cycles for a N-point DFT. The architecture is modular and makes possible computation of a 2N-point transform by a simple cascade of two identical N-point transform chips. The architecture is simple and regular in structure and is hence very attractive for VLSI implementation
Keywords :
VLSI; digital signal processing chips; discrete Fourier transforms; pipeline processing; 2N-point transform; DFT; VLSI architecture; clock cycles; discrete-Fourier transform; identical N-point transform chips; modular architecture; one-dimensional fully pipelined architecture; Clocks; Computer architecture; Delay; Discrete Fourier transforms; Discrete transforms; Hardware; Image processing; Signal processing; Student members; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-1760-2
DOI :
10.1109/MWSCAS.1993.343072
