DocumentCode :
2263605
Title :
Implementation of resilient packet ring nodes using network processors
Author :
Kirstädter, Andreas ; Hof, Axel ; Meyer, Walter ; Wolf, Erwin
Author_Institution :
Corp. Technol. & Commun., Siemens AG, Munchen, Germany
fYear :
2003
fDate :
20-24 Oct. 2003
Firstpage :
577
Lastpage :
582
Abstract :
Network processors offer a new flexibility for network applications and reduce the time to market for data processing systems. In this paper, we describe the changed development process of the data plane using the Motorola C-5 network processor. We implemented a resilient packet ring line card for a SDH cross connect. We show a solution for the support of different quality of service classes with a network processor and to achieve the necessary system stability. Additionally we carried out some simulations to verify the performance of a fairness algorithm over the ring and the system behavior.
Keywords :
local area networks; microprocessor chips; quality of service; synchronous digital hierarchy; Motorola C-5 network processor; data plane; data processing systems; network processors; quality of service; resilient packet ring; Add-drop multiplexers; Computational modeling; Data processing; Ethernet networks; Hardware; Process control; Quality of service; Standards development; Switches; Synchronous digital hierarchy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Local Computer Networks, 2003. LCN '03. Proceedings. 28th Annual IEEE International Conference on
ISSN :
0742-1303
Print_ISBN :
0-7695-2037-5
Type :
conf
DOI :
10.1109/LCN.2003.1243184
Filename :
1243184
Link To Document :
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