Title :
Built-in self repair by reconfiguration of FPGAs
Author :
Habermann, S. ; Kothe, R. ; Vierhaus, H.T.
Author_Institution :
Comput. Eng. Group, Brandenburg Univ. of Technol., Cottbus
Abstract :
Systems on a chip (SoCs) in safety-critical applications need features such as built-in self-test, on-line self-test and error compensation of transient faults. With ever-shrinking feature size, also built-in self-repair (BISR) may become a must. While BIST and BISR are well understood and frequently implemented for embedded memory blocks, BISR for random logic is by far an unsolved problem. Logic circuits based on field-programmable gate arrays (FPGAs) are a technology base that allows for functional reconfiguration in the field of application. In this paper we investigate on the possibilities and limitations of logic BISR for FPGAs
Keywords :
field programmable gate arrays; logic testing; reliability; system-on-chip; FPGA reconfiguration; SoC; built-in self repair; logic circuit; random logic; safety-critical applications; systems on a chip; Application software; Built-in self-test; Circuit faults; Field programmable gate arrays; Logic arrays; Logic devices; Reconfigurable logic; Routing; Signal synthesis; System-on-a-chip;
Conference_Titel :
On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International
Conference_Location :
Lake Como
Print_ISBN :
0-7695-2620-9
DOI :
10.1109/IOLTS.2006.13
