Design of a robust 8-bit microprocessor to soft errors

Author

Bastos, Rodrigo Possamai ; Kastensmidt, Fernanda Lima ; Reis, Ricardo

Author_Institution

Inst. de Informatica, Univ. Fed. do Rio Grande do Sul (UFRGS), Porto Alegre

fYear

0

fDate

0-0 0

Abstract

This work presents a fault-tolerant version of the mass-produced 8-bit microprocessor M68HC11. It is able to tolerate single event transients (SETs) and single event upsets (SEUs). Based on triple modular redundancy (TMR) and time redundancy (TR) fault tolerance techniques, a protection scheme was implemented at high level in the sensitive areas of the microprocessor by using only standard gates in order to save design time. Furthermore, fault-tolerant IC design issues and results in area and performance were compared with a non-protected microprocessor version

Keywords

fault tolerant computing; integrated circuit design; logic design; logic gates; microprocessor chips; redundancy; 8 bit; SET; SEU; TMR fault tolerance techniques; TR fault tolerance techniques; fault-tolerant IC design; microprocessor design; nonprotected microprocessor; single event transients; single event upsets; soft errors; time redundancy fault tolerance techniques; triple modular redundancy fault tolerance techniques; Application specific integrated circuits; Circuit faults; Clocks; Fault tolerance; Microprocessors; Protection; Redundancy; Robustness; Single event transient; Single event upset;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International

Conference_Location

Lake Como

Print_ISBN

0-7695-2620-9

Type

conf

DOI

10.1109/IOLTS.2006.21

Filename

1655548