A simple and efficient timing estimation algorithm for DS-CDMA systems

In traditional feedback structure of direct sequence spread spectrum (DS-SS) receiver, delay lock loop is a prevailing approach to estimate the timing error. However, in burst communication, it is hard for DLL to be in transient state or lock the signal with high accuracy. In this paper, an efficient feedforward PN code timing recovery scheme is proposed for DS-SS systems. The received signal after the chip-matched filter is two times over-sampled. The characteristics of DS-SS signal are explored to make the synchronization scheme efficient and simple in such a low sampling rate. Three sets of correlation values with different timing offsets are stored to estimate the code timing and carrier phase error. With very low computational complexity, the proposed scheme can make the performance approaches to the DS- SS systems with ideal synchronization in an AWGN channel.