DocumentCode
2263759
Title
Should Logic SER be Solved at the Circuit Level?
Author
Mak, T.M. ; Mitra, S.
Author_Institution
Intel Corporation
fYear
2006
fDate
10-12 July 2006
Firstpage
199
Lastpage
199
Abstract
SER is one of the problems associated with continued scaling. Traditionally, logic SER is solved at the system/architecture level (e.g., DMR, TMR, checkpointing/recovery). There has also been some work at the process level (e.g., SOI), but recently, there is also some research work on circuit level (e.g., cell hardening, BISER), but there has not been a wide spread adoption yet. Can logic SER be solved at the circuit level? Should they be? We have a team of experts from system, architecture and circuit area to debate this topic.
Keywords
Checkpointing; Circuit testing; Logic circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International
Print_ISBN
0-7695-2620-9
Type
conf
DOI
10.1109/IOLTS.2006.56
Filename
1655549
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