DocumentCode :
2264025
Title :
Area-efficient Reed-Solomon decoder design for 10-100 Gb/s applications
Author :
Yuan, Bo ; Li, Li ; Sha, Jin ; Wang, Zhongfeng
Author_Institution :
Inst. of VLSI Design, Nanjing Univ., Nanjing, China
fYear :
2009
fDate :
24-27 May 2009
Firstpage :
2681
Lastpage :
2684
Abstract :
With the extensive applications in high-speed communication systems, the current high-throughput Reed-Solomon decoders are required to achieve the target data rates from 10 Gb/s to 100 Gb/s with low hardware complexity. In this paper, pipeline interleaving inversionless Berlekamp-Massey (PI-iBM) algorithm and pipeline interleaving reformulated inversionless Berlekamp-Massey (PI-RiBM) algorithms for decoding Reed-Solomon codes are presented. Based on these two new algorithms PI-iBM and PI-RiBM Reed-Solomon decoders targeted at 10-100 Gb/s applications are developed. Compared with previously published works, the proposed designs can achieve very high throughput with relatively low hardware complexity. Thus they are well suited for modern high data rate communication systems.
Keywords :
Reed-Solomon codes; decoding; interleaved codes; pipeline processing; PI-iBM algorithm; Reed-Solomon decoder design; bit rate 10 Gbit/s to 100 Gbit/s; high-speed communication system; inversionless Berlekamp-Massey algorithm; pipeline interleaving; Computer architecture; Decoding; Delay; Equations; Hardware; Interleaved codes; Pipelines; Polynomials; Reed-Solomon codes; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
Type :
conf
DOI :
10.1109/ISCAS.2009.5118354
Filename :
5118354
Link To Document :
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