Title :
Decoding a family of dense codes using the Sum-Product Algorithm
Author :
Pérez-Chamorro, Jorge ; Seguin, Fabrice ; Lahuec, Cyril ; Jézéquel, Michel ; Le Mestre, Gerald
Author_Institution :
Electron. Dept., TELECOM Bretagne - Technopole, Brest, France
Abstract :
Cortex codes are a family of block codes with good minimum distance properties whose parity-check matrices are very dense. Digital implementations of Cortex decoders using standard decoding algorithms have not shown an acceptable performance. Motivated by the encoder structure, a new bipartite graph is introduced and exemplified for the Cortex construction of the extended Hamming code. The Cortex graph has longer girth and approximately 80% less cycles than the Tanner graph. A Cortex and an LDPC-like decoder were implemented for the same code using identical PMOS-based Gilbert multipliers. This makes them the first reported analog decoders using mainly PMOS transistors. The Cortex outperforms the LDPC-like decoder in bit error rate and at the same time saves 44% of die surface. The results are supported using data from a test chip designed for a 0.25 mum CMOS process.
Keywords :
CMOS integrated circuits; Hamming codes; block codes; decoding; error statistics; graph theory; matrix algebra; parity check codes; CMOS process; Cortex codes; LDPC-like decoder; PMOS transistors; PMOS-based Gilbert multipliers; Tanner graph; bipartite graph; bit error rate; block codes; decoding; encoder structure; extended Hamming code; parity-check matrices; size 0.25 mum; sum-product algorithm; Bipartite graph; Bit error rate; Block codes; Decoding; Joining processes; MOSFETs; Parity check codes; Sum product algorithm; Telecommunications; Testing;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118355