Realization of an airborne radar parallel signal processing system

Author

Junyi, Xu ; Xiutan, Wang ; Yingning, Peng

Author_Institution

Dept. of Electron. Eng., Tsinghua Univ., Beijing, China

fYear

2001

fDate

2001

Firstpage

792

Lastpage

795

Abstract

In order to fulfil real time signal processing tasks such as clutter rejection, moving target detection (MTD) and constant false alarm rate (CFAR) control in airborne radar, an airborne radar parallel signal processing system (ARPS2) is proposed with DSP chips as its kernel processing nodes. The DSP chips are used with parallel architecture. Each node has its private input and output memory. It adopts several parallel techniques, such as parallel storage, parallel processing, parallel code loading and parallel data organization to achieve high efficiency. It has a simple structure, excellent flexibility and easiness in developing. ARPS2 is going to be applied to an airborne radar. It can also be applied to perform high-speed real time signal processing algorithms in other kinds of radar

Keywords

airborne radar; digital signal processing chips; interference suppression; parallel architectures; parallel processing; radar clutter; radar detection; radar signal processing; CFAR control; DSP chips; airborne radar; clutter rejection; constant false alarm rate control; moving target detection; parallel architecture; parallel code loading; parallel data organization; parallel processing; parallel signal processing system; parallel storage; private memory; real time radar signal processing; Airborne radar; Clutter; Control systems; Digital signal processing chips; Kernel; Object detection; Parallel architectures; Parallel processing; Radar signal processing; Real time systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Radar, 2001 CIE International Conference on, Proceedings

Conference_Location

Beijing

Print_ISBN

0-7803-7000-7

Type

conf

DOI

10.1109/ICR.2001.984832

Filename

984832