Title :
Data dependent optimization of ROM structures
Author :
Vallapaneni, Venkat R. ; Prasad, A.V.S.S.
Author_Institution :
LSI Technol. India Pvt. Ltd., India
Abstract :
Read only memories (ROMs) occupy 40% to 80% of the area in most of the current generation system on chips (SoCs). Hence, any reduction in ROM area could effectively result in chips with low die area. A novel optimized ROM structure based on data contents is proposed in this paper. Customized address decoder and memory core are designed based on data contents leading to an area reduction of up-to 60% and considerable reduction in power and access times. Analysis of overall transistor count is performed for a few real-life SoC applications and also for random data.
Keywords :
MOSFET; decoding; low-power electronics; read-only storage; system-on-chip; NMOS transistor; customized address decoder; data content; memory core; overall transistor count performance; power reduction; read only memory structure optimization; system on chips; Circuit synthesis; Decoding; Design optimization; Equations; Large scale integration; Moore´s Law; Performance analysis; Read only memory; System-on-a-chip; Transistors;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118371
