Title :
High-performance, low-power design techniques for dynamic to static logic interface
Author :
Jiang, June ; Lu, Kan ; Ko, Uming
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
To optimize performance and power of a processor with both precharged and static circuit styles, a self-timed modified cascode latch (MCL) is proposed for dual-rail domino to static logic interface. Compared to conventional self-timed cascode and cross-coupled NAND latches, the innovative MCL achieves the highest performance and lowest power dissipation with reasonable noise immunity. Ease of embedding logic functions in these self-timed latches is also studied. For interfacing single-rail domino to static logic, the pseudo-inverter latch (PIL) is the most power efficient latch when compared with the conventional transparent and cross-coupled NAND latches. Based on a 0.18 /spl mu/m CMOS nominal process with a 1.6 V supply voltage, effects on these latches´ power dissipation and delay from scaling supply voltage and output load are presented respectively.
Keywords :
CMOS logic circuits; delays; integrated circuit design; integrated circuit noise; logic design; timing; 0.18 micron; 1.6 V; CMOS process; delay; dual-rail domino to static logic; dynamic to static logic interface; low-power design techniques; noise immunity; output load scaling; power dissipation; pseudo-inverter latch; self-timed modified cascode latch; single-rail domino to static logic; supply voltage scaling; CMOS logic circuits; CMOS process; Circuit noise; Delay effects; Latches; Logic circuits; Logic design; Logic functions; Power dissipation; Voltage;
Conference_Titel :
Low Power Electronics and Design, 1997. Proceedings., 1997 International Symposium on
Conference_Location :
Monterey, CA, USA
Print_ISBN :
0-89791-903-3
