Title :
Evaluation of transistor property variations within chips on 300 mm wafers using a new MOSFET array test structure
Author :
Izumi, N. ; Ozaki, Hiroaki ; Nakagawa, Yukihiro ; Kasai, Naoki ; Arikado, T.
Author_Institution :
Process Module Program, Semicond. Leading Edge Technol. Inc., Tsukuba, Japan
fDate :
30 Sept.-2 Oct. 2003
Abstract :
A new test structure has been designed to evaluate fluctuations of transistor properties, both within a chip and on a 300 mm wafer. It was observed that threshold voltage (Vth) variations increased with the reduction of the channel area. A difference was also observed in the standard deviation (σvt) between NMOS and PMOS. It was found that it was important to control CD and to improve roll-off characteristics in order to reduce Vth variations.
Keywords :
MOSFET; 300 mm; MOSFET array test; n-channel MOS; p-channel metal-oxide-semiconductor; standard deviation; threshold voltage; transistor property variations; Circuit testing; Current measurement; Electrical resistance measurement; Fluctuations; MOSFET circuits; Semiconductor device measurement; Semiconductor device testing; System testing; Voltage; Wiring;
Conference_Titel :
Semiconductor Manufacturing, 2003 IEEE International Symposium on
Print_ISBN :
0-7803-7894-6
DOI :
10.1109/ISSM.2003.1243238
