Parametric delay and area models for adders

Author

Williams, Derek E. ; Swartzlander, Earl E., Jr.

Author_Institution

IBM Corp., Austin, TX, USA

fYear

1993

fDate

16-18 Aug 1993

Firstpage

863

Abstract

This paper derives delay and area estimates for the four major adder types: ripple carry, carry skip, carry select, and carry lookahead. The models take into consideration gate area variation and gate delay variation as a function of fan-in for various size AND and OR gates. In addition, layout considerations are also modeled. Equations for the time to the final sum and carry bit are derived for all the adders. In addition, equations for the area of the various adders are derived. Naive (or simple) models that do not take into account varying gate delays and area are provided for comparison. In conclusion, the models are applied to 16 bit adders for comparison and some suggestions are made for extending the models

Keywords

adders; carry logic; delays; digital arithmetic; integrated circuit layout; integrated circuit modelling; integrated logic circuits; logic gates; AND gates; OR gates; adders; area estimates; carry lookahead; carry select; carry skip; delay estimates; gate area variation; gate delay variation; layout; parametric area models; parametric delay models; ripple carry; Added delay; Delay estimation; Equations; Inverters; Multiplexing; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on

Conference_Location

Detroit, MI

Print_ISBN

0-7803-1760-2

Type

conf

DOI

10.1109/MWSCAS.1993.343205

Filename

343205