• DocumentCode
    2264891
  • Title

    An analytic method for calculating current sharing in emitter-coupled bipolar transistors

  • Author

    Brauer, E.J. ; Kang, S.M.

  • Author_Institution
    Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
  • fYear
    1993
  • fDate
    16-18 Aug 1993
  • Firstpage
    887
  • Abstract
    This paper describes an analytic method for calculating current sharing in emitter coupled bipolar transistors. We use a simplified Ebers-Moll transistor model to approximate current sharing by first ignoring the terminal resistances. We then derive an analytic equation to compensate the collector currents in order to include the effect of terminal resistances. The model is accurate for a wide range of device parameters. Our method has applications in emitter-coupled logic functional verification and timing simulation where current sharing in emitter-coupled transistors must be calculated
  • Keywords
    bipolar logic circuits; bipolar transistors; emitter-coupled logic; semiconductor device models; ECL functional verification; Ebers-Moll transistor model; analytic method; collector currents compensation; current sharing; emitter-coupled bipolar transistors; emitter-coupled logic; terminal resistances; timing simulation; Bipolar transistors; Circuit simulation; Computational modeling; Delay; Equations; Logic devices; Resistors; SPICE; Timing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
  • Conference_Location
    Detroit, MI
  • Print_ISBN
    0-7803-1760-2
  • Type

    conf

  • DOI
    10.1109/MWSCAS.1993.343210
  • Filename
    343210